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Boot & Memory
GDT, IDT & Mode Switching
Two tables decide what the CPU may do and where interrupts go: the Global Descriptor Table (GDT) and the Interrupt Descriptor Table (IDT). Both are arrays of 8-byte entries whose fields are scattered across the bits for historical reasons, and both are loaded with one instruction (lgdt, lidt). In this lesson your program encodes and decodes those exact 64-bit values, the same ones a kernel writes at boot.
Why segmentation still exists
The 286 and 386 protected memory with segments: a descriptor gives a base, a limit and access rights. Every modern OS sets up the flat model, base 0 and limit 4 GiB for everything, and does real protection with paging. But the CPU still requires the table: the privilege level in CS (the CPL) comes from the descriptor your code selector points at, and the syscall and interrupt paths load segments from it. A 64-bit kernel ignores base and limit, but code segments still need the L flag.
The segment descriptor
63 56 55 52 51 48 47 40 39 16 15 0
+----------+------+----------+----------+------------+----------+
| base |flags | limit | access | base | limit |
| 31..24 | 4 b | 19..16 | byte | 23..0 | 15..0 |
+----------+------+----------+----------+------------+----------+
The access byte is P DPL(2) S Type(4): bit 7 present, bits 6-5 privilege level, bit 4 S (1 for code and data, 0 for system entries such as the TSS), and for S = 1 bit 3 selects code (1) or data (0). The flags nibble is G D/B L AVL: bit 3 granularity (limit counted in 4 KiB units), bit 2 32-bit default, bit 1 long-mode code, bit 0 spare.
Worked example, the classic flat ring-0 code segment: base 0, limit 0xFFFFF, access 0x9A (present, DPL 0, code, readable), flags 0xC (4 KiB granularity, 32-bit). Place the pieces: limit 15..0 is FFFF; base 23..0 is 000000; access 9A; limit 19..16 is F followed by the flags C, giving the byte CF; base 31..24 is 00. Read from the top: 00 CF 9A 00 00 00 FF FF, that is 0x00CF9A000000FFFF. Its siblings differ only in the access byte: 92 kernel data, FA user code (DPL 3), F2 user data. A 64-bit kernel code segment uses flags 0xA (granularity plus long mode): 0x00AF9A000000FFFF.
With the G flag set the effective size is (limit << 12 | 0xFFF) + 1 bytes, so limit 0xFFFFF means 4 GiB.
Selectors
A segment register holds a 16-bit selector, not the descriptor: index << 3 | TI << 2 | RPL. Index 1 in the GDT at RPL 0 is 0x08 (the usual kernel code), index 2 is 0x10. User code at index 3 with RPL 3 is 0x1B, user data at index 4 is 0x23. Entry 0 is the null descriptor and must exist.
The IDT: 256 doorways
Vectors 0-31 are CPU exceptions (14 is the page fault), the rest are yours. Each 32-bit gate is also 8 bytes:
63 48 47 40 39 32 31 16 15 0
+------------+----------+-------+-----------+-----------+
| offset | type/ | zero | selector | offset |
| 31..16 | attr | | | 15..0 |
+------------+----------+-------+-----------+-----------+
The type/attribute byte is P DPL 0 Type: type 0xE is a 32-bit interrupt gate (clears IF on entry), 0xF a trap gate (leaves IF alone). 0x8E is the standard kernel gate. 0xEE has DPL 3, so user code may invoke it with int; that is how int 0x80 system calls work. For handler 0x00101234 in selector 0x08 with attribute 0x8E the gate is 0x00108E0000081234.
The switching sequence
Real mode to protected mode: enable the A20 line, lgdt, set CR0.PE, far-jump to reload CS from the new table. Protected to long mode: build page tables, set CR4.PAE, point CR3 at them, set EFER.LME, set CR0.PG, and far-jump into a code segment with the L flag.
Common mistakes
- Putting the flags nibble in the wrong place: it sits above limit 19..16, never beside the access byte.
- Writing the base or limit as one contiguous field. Split them.
- Forgetting that a selector is
index << 3, so index 1 is0x08, not0x01. - Reading
Sas present: bit 7 is present, bit 4 isS.
Your exercise
Five commands encode and decode descriptors, gates and selectors. The starter handles input and output; you write the bit packing.
Discussion
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