Build a CPU (RISC-V)
Build a RISC-V RV32I simulator: register file, instruction decoding (R/I/S/B/U/J formats), ALU + load/store + branch + jump execution, calling convention, syscalls, and the fetch-decode-execute loop. Same architecture as Spike, QEMU's RISC-V mode.
advanced10 lessons4 chapters10 graded exercisesPython
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What you’ll have built
Chapter by chapter. Every step is a graded exercise.
- Architecture Basics
- Instruction Decoding
- Execution
- Production
Starts in Python — solve in the language you choose in the editor, same tests either way.
Curriculum
4 chapters, 10 lessons. Each lesson is a short read, one graded exercise, and a quiz.
- 1What a CPU DoesRead · exercise · quiz
- 2RISC-V Instruction FormatsRead · exercise · quiz
- 3Memory LayoutRead · exercise · quiz
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