RISC-V Instruction Formats

Every RV32I instruction is 32 bits. There are six formats:

R-type (register-register, e.g. ADD, SUB):
[funct7   ][rs2 ][rs1 ][funct3][rd  ][opcode]
 31     25 24 20 19 15 14   12 11 7  6     0

I-type (immediate, e.g. ADDI, LW, JALR):
[imm[11:0]      ][rs1 ][funct3][rd  ][opcode]
 31           20 19 15 14   12 11 7  6     0

S-type (store, e.g. SW):
[imm[11:5]][rs2 ][rs1 ][funct3][imm[4:0]][opcode]

B-type (branch, e.g. BEQ):
[imm[12]|imm[10:5]][rs2 ][rs1 ][funct3][imm[4:1]|imm[11]][opcode]

U-type (upper immediate, e.g. LUI, AUIPC):
[imm[31:12]                            ][rd  ][opcode]

J-type (jump, e.g. JAL):
[imm[20]|imm[10:1]|imm[11]|imm[19:12]  ][rd  ][opcode]

Opcodes (low 7 bits) tell you the format:

• 0x33: R-type ALU.
• 0x13: I-type ALU.
• 0x03: I-type load.
• 0x23: S-type store.
• 0x63: B-type branch.
• 0x37: U-type LUI.
• 0x17: U-type AUIPC.
• 0x6F: J-type JAL.
• 0x67: I-type JALR.
• 0x73: SYSTEM (ECALL, EBREAK).

Decoder:

Immediates are sign-extended and assembled from scattered bit positions:

Tedious but mechanical. Get it right once.