ALU Instructions

Arithmetic + logic operations. Two flavors:

• R-type: rd = rs1 OP rs2. (ADD, SUB, AND, OR, XOR, SLL, SRL, SRA, SLT, SLTU)
• I-type: rd = rs1 OP imm. (ADDI, ANDI, ORI, XORI, SLLI, SRLI, SRAI, SLTI, SLTIU)

Operations:

• ADD / ADDI: sum.
• SUB: difference (R-type only; for SUBI use ADDI with negative imm).
• AND / OR / XOR: bitwise.
• SLL / SLLI: shift left logical.
• SRL / SRLI: shift right logical (zero-fill).
• SRA / SRAI: shift right arithmetic (sign-fill).
• SLT / SLTI: set less than (signed).
• SLTU / SLTIU: set less than unsigned.

Distinction: funct7 + funct3 select the specific op within the R-type opcode.

funct3=0, funct7=0x00 → ADD
funct3=0, funct7=0x20 → SUB
funct3=4, funct7=0x00 → XOR
...

Overflow: RISC-V spec ignores. Wraps modulo 2^32. C compilers know this and emit checks if needed (signed overflow is UB in C, but the underlying instruction wraps).

Pseudoinstructions: assembler shorthand that maps to one or more real instructions.

• MV rd, rs → ADDI rd, rs, 0.
• LI rd, imm → ADDI (small) or LUI + ADDI (larger).
• NOP → ADDI x0, x0, 0.
• NOT rd, rs → XORI rd, rs, -1.

These don't exist in the encoding. The assembler emits the real instructions.