Production CPUs & Simulators

Real silicon vs simulators:

Silicon optimizations (skipped in toy):

• Pipelining: 5+ stages (fetch, decode, execute, memory, writeback) in parallel. ~1 instruction per cycle ideal.
• Superscalar: multiple instructions per cycle.
• Out-of-order execution: reorder instructions for ILP.
• Branch prediction: speculate branches before resolved. Spectre-class attacks exploit speculation.
• Caches: L1 (~32 KiB, ~1 cycle), L2 (~256 KiB, ~10), L3 (~8 MiB, ~30), DRAM (~200).
• TLB: caches page table walks.
• MMU: virtual memory, paging, protection.
• Interrupts: timer, devices.
• Privilege modes: user, supervisor, machine.
• SIMD: vector instructions (SSE, AVX, NEON, RVV).
• Atomics: LR/SC or CAS.

A toy that runs unmodified RISC-V code passes most tests but is hundreds of times slower than real silicon.

Production simulators:

• QEMU: full system emulation (CPU + devices + OS). JIT-translates guest to host. Used for VMs, embedded dev.
• Spike: official RISC-V simulator. ISA-accurate.
• Renode: embedded simulator. Includes peripherals.
• gem5: cycle-accurate simulator for research.
• Renode, Verilator: HDL-based simulators (closer to hardware).

FPGA prototypes:

• Synthesize RISC-V Verilog onto an FPGA (Lattice ECP5, Xilinx Artix).
• Run real software at slower clock speed.
• Bridge between simulator and silicon.

Real RISC-V chips:

• SiFive (FU740, P870 etc.).
• Kendryte K210.
• ESP32-C3 (RISC-V cores).
• Western Digital, Alibaba T-Head: server-grade.

Cycle-accurate vs functional simulators:

• Functional: ISA-correct; runs programs.
• Cycle-accurate: tracks pipeline, predicts performance. Slower.
• Toy is functional only.

Use cases for our toy:

• Educational.
• Verifying compiler output.
• Tiny embedded software regression.

Don't roll your own for production. Use QEMU or commercial.

The build is the lesson: by the end, you understand WHY x86-64 has prefixes, segments, complex addressing — RISC-V's simplicity makes you appreciate the elegance.